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Technical Specification |
Remarks |
| Number Of Layer |
1~8 |
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| Material |
FR4,CEM1,CEM3,ARLON |
Special Material On Request
(BT,Roger,Telfon etc.) |
| Finish Board Thickness |
0.20mm~6.00mm
(8mil~236mil) |
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| Minimum Core Thickness |
0.1mm(4 mil) |
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| Copper Thickness |
min.1/2 OZ,max.3 OZ |
Selective Plating |
| Min.Trace Wide &Line Space |
Single Sided |
0.100mm(4 mil) |
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| Double Sided |
0.100mm(4 mil) |
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| Min.Hole Diameter |
Drilling /PTH |
φ0.25mm(10 mil) |
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| Punching |
φ0.90mm(36 mil) |
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|
Dimension
Tolerance |
Hole Position |
±0.075 ( 3 mil ) |
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| Conductor Width(W) |
±10% |
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| Hole Diameter(H) |
±0.03 mm ( 1.2 mil )
[ With PTH ±0.05 mm ( 2 mil ) ] |
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| Outline Dimension |
±0.10 mm ( 4 mil ) |
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Conductors & Outline
(C-O) |
±0.15 mm ( 6 mil )
|
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| Warp and Twist |
0.70%
|
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| Surface Treatment On Land Area |
"Nickel / Gold Plate or Hot Air Levelling "
|
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| Insulation Resistance |
10KΩ~20MΩ(typical:5MΩ)
|
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| Continuity |
<50Ω(typical:25Ω)
|
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| Test voltage |
250V(max)
|
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| V-Cutting |
Panel Size
|
110 mm X 100 mm ( min. )
|
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Board Thickness
|
0.40 mm (16mil) min.
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Remain Thickness
|
0.20 mm (8mil) min.
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Tolerance
|
±0.1 mm(4mil)
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Groove Width
|
0.50 mm (20mil) max.
|
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Groove to Groove
|
15 mm (590mil) min.
|
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Groove to Trace
|
0.45 mm(18mil) min.
|
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Slot
|
Slot size tol.L≥2W
|
L：±0.15(6mil) W：±0.10(4mil) |
Where:(1)L=Length of slot
(2)W=Width of slot
"(3)Min.drill bit size for multi-hit
drilling is 0.60mm" |
NPTH slot(mm) L：±0.125(5mil)
W：±0.075(3mil) |
| Minimum spacing between hole edge to hole edge |
Hole diameter(mm)
|
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0.30-1.60
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0.10mm(4mil) |
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1.61-6.50
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0.15mm(6mil)
|
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Minimum spacing between hole edge to circuitry pattern
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PTH hole: 0.13mm(5mil)
|
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NPTH hole: 0.18mm(7mil)
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| Image transfer Registration tolerance |
Circuit pattern vs.index hole
|
±0.075(3mil) |
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Circuit patten vs. 2nd drill hole
|
±0.10(4mil) |
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| Registration toleranceof front/back image |
Front image vs back image
|
0.075mm(3mil) |
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Multilayers
|
Layer-layer misregistration
|
4layers:0.15mm(6mil)max. |
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| 6layers:0.2mm(8mil)max |
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8layers:0.25mm(10mil)max.
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Min. spacing between board outline to circuitry pattern of an inner-layer
|
0.225mm(9mil) |
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Min. board thickness
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4layers:0.35mm(14mil) |
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6layers:0.60mm(23.6mil)
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| 8layers:1.00mm(40mil) |
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Board thickness tolerance
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4layers:+/-0.13mm(5mil)
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6layers:+/-0.15mm(6mil)
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8layers:+/-0.15mm(6mil)
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Impedance control
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Typical: 50Ω+/-10%
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